#define WDT_MODE_REG 0xFFFFFD44
#define WDT_MODE (*((volatile unsigned int *)WDT_MODE_REG))

#define PMC_CKGR_MOR_REG 0xFFFFFC20
#define PMC_CKGR_MOR (*((volatile unsigned int *)PMC_CKGR_MOR_REG))

#define PMC_PLLR_REG 0xFFFFFC2C
#define PMC_PLLR (*((volatile unsigned int *)PMC_PLLR_REG))

#define PMC_SR_REG 0xFFFFFC68
#define PMC_SR (*((volatile unsigned int *)PMC_SR_REG))

#define MC_FWS_1FWS ((unsigned int) 0x1 <<  8) 

#define PMC_MCKR  (*((volatile unsigned int *) 	0xFFFFFC30)) // (PMC) Master Clock Register

#define PMC_MOSCS		(1)
#define PMC_LOCK		(1 << 2) 
#define PMC_MCKRDY		(1 << 3)
#define PMC_CSS_PLL_CLK (0x3) 
#define PMC_PRES        (0x7 <<  2) 
#define PMC_PRES_CLK_2  (0x1 <<  2) // (PMC) Selected clock divided by 2

#define CKGR_DIV_MASK        ((unsigned int) 0xFF)
#define CKGR_PLLCOUNT_MASK   ((unsigned int) 0x3F <<  8)
#define CKGR_MUL_MASK        ((unsigned int) 0x7FF << 16)
#define CKGR_MOSCEN           (1)
#define CKGR_OSCOUNT_MASK    ((unsigned int) 0xFF <<  8)


/* TODO: ADD registers for PIO */

#define MC_FMR_REG 0xFFFFFF10
#define MC_FMR (*((volatile unsigned int *)MC_FMR_REG))

int main(void)
{
	unsigned int nCnt=0;
	WDT_MODE = (unsigned int)1 << 15; /* Watch dog timer off, WDDIS bit */

	/* (MC) 2 cycles for Read, 3 for Write operations */
	MC_FMR = MC_FWS_1FWS; /* Only needed if executed from flash, sets wait states */

	//* Set MCK at 48 054 841
	// 1 Enabling the Main Oscillator:
	// SCK = 1/32768 = 30.51 uSecond
	// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
	// --> use 8

	PMC_CKGR_MOR = (( CKGR_OSCOUNT_MASK & (0x06 <<8) | CKGR_MOSCEN )); /* set main oscillator */

	while( !(PMC_SR & PMC_MOSCS) ); /* Wait for MOSCS */

	// Main Clock (MAINCK from crystal oscillator) = 18432000 hz (see AT91SAM7-EK schematic)
	// MAINCK / DIV = 18432000/14 = 1316571 hz

	// PLLCK = 1316571 * (MUL + 1) = 1316571 * (72 + 1) = 1316571 * 73 = 96109683 hz
	//
	// PLLCOUNT = number of slow clock cycles before the LOCK bit is set
	//            in PMC_SR after CKGR_PLLR is written.
	//
	// --> PLLCOUNT = 10
	// --> MUL = 72
	// --> DIV = 14

	PMC_PLLR = ((CKGR_DIV_MASK & 14) | (CKGR_PLLCOUNT_MASK & (10<<8)) | (CKGR_MUL_MASK & (72<<16)));


	// Wait the startup time (until PMC Status register LOCK bit is set)
	while( !(PMC_SR & PMC_LOCK) );

	// PMC Master Clock (MCK) Register setup
	//
	// CSS = 3 (PLLCK clock selected)
	//
	// PRES = 1 (MCK = PLLCK / 2) = 96109683/2 = 48054841 hz
	//
	// Note: Master Clock MCK = 48054841 hz (this is the CPU clock speed)
	// result: AT91C_PMC_MCKR = 0x00000007 (Master Clock Register)
	PMC_MCKR = PMC_CSS_PLL_CLK | PMC_PRES_CLK_2;

	while( !(PMC_SR & PMC_MCKRDY) ); /* Wait for PMC_MCKRDY */

	/* TODO: ADD code to configure PORT */

	while (1) {

		/* TODO: ADD code to set LED pin, note the inverted logics */
		nCnt = 0; 
		while(nCnt++ < 200000); /* Dummy loop for the blink */

		/* TODO: ADD code to clear LED pin */
		nCnt = 0; 
		while(nCnt++ < 200000); /* Dummy loop for the blink */
	}
}