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November 20 Workshop on Wireless Vehicular Communications
November 19 Halmstad Colloquium talk - Vehicular Channel Characterization for Dependable Intelligent Transport Systems
Professor Christoph Mecklenbräuker, Institute of Telecommunications, TU Vienna
October 22 Seminar on Quality of prognostics and health management systems
Ahmed Mosallam, ph.d. student at University of Franche-Comte, FEMTO-ST
October 15 Seminar on Classification of moving target by radar using spectrum based features
Pavlo Molchanov from Tampere University of Technology, Finland
Abstract and about
June 20 Seminar in Modeling by professor Michel Chaudron, Chalmers university of technology and Leiden university
Is Modeling Any Good? Empirical Evidence on Modeling in Software Development
Modeling is a common part of modern day software engineering practice Little evidence is known about how models are used and if/how they help in producing better software. In this talk I will present highlights from the last decade of research in the area of software modeling using UML.
Topics that was addressed:
Professor Chaudron's research interests are in: software architecture, software design, software modeling, software composition and empirical studies in software engineering.
June 17-19 Smart Grid workshop 2013
June 7 Doctoral thesis defence, Annette Böhm defended her doctoral thesis:
Delay-sensitive wireless communication for cooperative driving applications
Opponent: Prof. Javier Gozálvez Sempere, University Miguel Hernández, Spain.
Professor Paul Davisson, Malmö University
Professor Ulf Körner, Lund University
Professor Mohammadreza Mousavi, Halmstad University
Professor Christer Åhlund, Luleå Technical University, substitute
Chair person: Professor Bertil Svensson, Halmstad University
June 3-5 Summer school in Testing
May 15 Halmstad colloquium talk - On YouTube
Autonomy is overrated: Towards shared human-machine control of vehicles and other mechanical systems
Dr. Karl Iagnemma, Massachusetts Institute of Technology, USA and Halmstad university
Abstract and bio (pdf, 34.9 kB)
May 5 Seminar
Dr. Boris Bellalta at Universitet Popeu Fabra, Spain, on Next Generation WLANs
April 16 Halmstad Colloquium talk - On YouTube
Model-based Design of Cyber-Physical Systems: Lessons learned
Professor Janos Sztipanovits, Vanderbilt University, Nashville, Tennessee, USA
April 15 Ph.D. defence
Katrin Sjöberg defended her ph.d. thesis:
Medium access control for vehicular ad hoc networks - Abstract (pdf, 138.2 kB)
Opponent: Dr. John Kenney
Professor Anna Brunström, Karlstads university
Dr. Stefan Parkvall, Ericsson Research, Kista, Stockholm
Professor Petar Popovski, Aalborg university, Aalborg, Danmark
Chair: Professor Bertil Svensson, Halmstad university
Main supervisor: Professor Erik Ström, Chalmers university of technology, Göteborg
Assistant supervisor: Docent Elisabeth Uhlemann, Mälardalens university, Västerås
April 15 Halmstad Colloquium talk - On YouTube
A Linear Adaptive Control Approach to Congestion Management in Cooperative ITS
Dr John Kenney från Toyota, Mountain View, CA, USA
February 4-5 CAISR workshop and meeting with the partners
Presentation of ongoing projects and other activities. Link to CAISRs website
January 14 Talk by Harshavardhan Kittur
Hardware Acceleration of Robust Header Compression (RoHC)
With the proliferation of Long Term Evolution (LTE) networks, many cellular carriers are embracing theemerging eld of mobile Voice over Internet Protocol (VoIP). The robust header compression (RoHC) frame-work was introduced as a part of the LTE Layer 2 stack to compress the large headers of the VoIP packetsbefore transmitted over LTE IP-based architectures. The headers, which are encapsulated Real-time Trans-port Protocol (RTP)/User Datagram Protocol (UDP)/Internet Protocol (IP) stack, are large compared tothe small payload. This header-compression scheme is especially useful for ecient utilization of the radiobandwidth and network resources.
In LTE base-station implementation, RoHC is a processing intensive algorithm that may prevent the LTEsystem from catering to a full capacity (number of users). In this article, A hardware-software and afull-hardware solutions are proposed targeting LTE base-stations to accelerate this computational intensivealgorithm and enhance the throughput and the capacity of the system. The results of both solutions arediscussed and compared with respect to the design metrics like throughput, capacity, power consumption,area and exibility. This comparison is instrumental in taking architectural level trade-o decisions in-orderto meet the present day requirements and yet be ready to support future evolution.
In terms of throughput, a gain of 20% (throughput of 6250 packets/sec) is achieved in the HW-SW solutioncompared to the SW-Only solution by implementing the Cyclic Redundancy Check (CRC) and the LeastSignicant Bit (LSB) encoding blocks as hardware accelerators . Whereas, a Full-HW implementation leadsto a throughput of 45 times (throughput of 244000 packets/sec) the throughput of the SW-Only solution.Finally, when both the solutions are synthesized on Altera's Arria II GX FPGA, the full-HW solutionconsumes more Lookup Tables (7477 ALUTs) when compared to HW-SW solution (2578 ALUTs) and alsothey consumes 0.9 and 1.5 Watts of power, respectively.
January 11 Talk by Süleyman Savas
Implementation and Evaluation of MPEG-4 Simple Profile Decoder on a Massively Parallel Processor Array
The high demand of the video decoding has pushed the developers to implement the decoders on parallel architectures. This thesis provides the deliberations about the implementation of an MPEG-4 decoder on a massively parallel processor array (MPPA), Ambric 2045, by converting the CAL actor language implementation of the decoder. This decoder is the Xilinx model of the MPEG-4 Simple Profile decoder and consists of four main blocks; parser, acdc, idct2d and motion. The parser block is developed in another earlier thesis work and the rest of the decoder, which consists of the other three blocks, is implemented in this thesis work. Afterwards, in order to complete the decoder, the parser block is combined with the other three blocks.
Several methods are developed for conversion purposes. Additionally, a number of other methods are developed in order to overcome the constraints of the ambric architecture such as no division support. At the beginning, for debugging purposes, the decoder is implemented on a simulator which is designed for Ambric architecture. Finally the implementation is uploaded to the Ambric 2045 chip and tested with different input streams. The performance of the implementation is analyzed and satisfying results are achieved when compared to the standards which are in use in the market. These performance results can be considered as satisfying for any real-time application as well. Furthermore, the results are compared with the results of the CAL implementation, running on a single 2 GHz i7 intel processor, in terms of speed and efficiency. The Ambric implementation runs 4.7 times faster than the CAL implementation when a small input stream (300 frames with resolution of 176x144) is used. However, when a large input stream (384 frames with resolution of 720x480) is used, the Ambric implementation shows a performance which is approximately 32 times better than the CAL implementation, in terms of decoding speed and throughput. The performance may increase further together with the size of the input stream up to some point.