Active RFID - VLSI Architectures for Small-Area, Low-Power Wireless Devices
|Duration:||March, 2005 - March, 2010|
|Senior researchers:||Bertil Svensson, Lars Bengtsson|
|Ph.D. student:||Björn Nilsson|
|Partners:||Free2move and Chalmers University of Technology|
|Extended abstract:||Link to extended abstract (pdf, 108.1 kB)|
|Link to project web site:|
Active RFID (Radio Frequency IDentification) tags need continuous power to operate. Production needs to be optimized for this type of product. Low production cost is a key factor, thus the number of dies to be mounted is critical. Another important issue is to reduce the area of the radio parts of the design to achieve better scalability. To reduce power consumption, low duty cycle operation modes are used. The bottleneck to get long battery life of a tag is the power consumption of the radio transceiver. The production cost depends on the number of components that must be mounted. Our aim is a low-area single chip mixed-signal solution instead of today's multi chip solution with a number of external components. A target price per tag-device must be in the fifty cent region to meet market demands.
Thus, the aim of this project is investigation, development and evaluation of cost efficient RF mixed-signal VLSI architectures for active RFID tags. Very low power consumption is necessary for long life-time; average in µW region is the target. Radio protocols enabling minimal power requirements and data communication algorithms to reduce the need of data redundancy is another prerequisite.