CERES Research projects

Background
It is today feasible to integrate more than one billion transistors on a single silicon chip. According to the International Technology Roadmap for Semiconductors (ITRS), the number of processor cores per chip will likely rise above one hundred in the next couple of years. The SMECY consortium anticipates that recently emerged multi-core technologies will rapidly develop to massively parallel computing environments, which in a few years will extensively penetrate the embedded computing industry.

Purpose
The mission of the SMECY project is to develop new system design and development technologies enabling the exploitation of many (100s) core architectures. Multi-core technologies are strategic for industry in all areas of embedded systems. One of the grand challenges with multi-core technology is to develop efficient design and development tools for multi-core architectures for various resource-constrained embedded system applications, such as consumer electronics, wireless communication and transportation systems.

Goals
The joint goals of SMECY are to develop new programmable architectural solutions based on multi-core technology, and associated supporting tools in order to master complete system design of future smart multi-core embedded systems. The hardware platforms and the development tools developed in the project will be demonstrated and evaluated for a certain set of representative applications provided by industrial partners of SMECY, such as radar systems and energy efficient wireless communication systems.
 
Funding
The project is funded within the ARTEMIS Joint Undertaking, which means that EU funding and national funding from the participating countries are coordinated. The project has a total budget of 20 399 K€ (EU funding: 3 406 K€, National funding: 6 474 K€, Partners´ own funding: 10 519 K€). The funding to CERES amounts to about 480 K€ (about 4.8 MSEK).