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CERES research projects

Project:

 

Embedded Parallel Computing - EPC

Duration: June 2007 - May 2010
Contact: Bertil Svensson
Senior researchers: Bertil Svensson, Veronica Gaspes, Hoai Hoang Bengtsson, Jerker Bengtsson, and Tony Larsson
Ph.D. students: Zain-ul-Abdin, Gordon Ononiwu (guest)
Partners: Saab Microwave Systems, Ericsson AB and Combitech AB
Extended abstract: Link to extended abstractPDF (pdf, 84.2 kB)
Link to project web site: More information about EPC
DESCRIPTION:

Purpose
Understanding parallel architectures and their usage is an important part of the CERES research program on Cooperating Embedded Systems. The project addresses the efficient use of parallel and reconfigurable computing structures in embedded high-performance applications. The work in the project is equally shared between the university researchers on one side and the industrial partners on the other.

Goals
The overall goal of the project is to understand which overall (hardware and software) architectures are best suited for a given application domain, as well as to find efficient ways of writing programs / mapping applications that execute efficiently on parallel/reconfigurable computing systems. The architectures, methods and tools shall be demonstrated, tested and evaluated on a common parallel platform with great flexibility.     
The project does not address general purpose processing; rather it is oriented towards the needs of high-performance embedded signal processing applications.     
The Project has four main “threads", each with its own goal. A fifth thread relates to the common platform for demonstration, test and evaluation. A sixth thread aims at joint knowledge development in a structured way.

Thread 1.
Stream processing architectures and languages with applications in baseband processing Goal: To develop language based tools that enable efficient execution of baseband processing al-gorithms on programmable array architectures.

Thread 2.
Programming of reconfigurable chip architectures Goal: To explore well established computation models and devise new design methods based on these models to — for selected streaming application(s) — program the emerging class of recon-figurable chip architectures with varying granularity.

Thread 3.
Methods for coordination of signal processing components Goal: To develop methods for design of high performance signal processing software that is port-able to several parallel platforms. The methods should: be based on a high-level resource and communication model; enable reuse of service components via suitable interfaces; and support dynamic coordination and reconfiguration of such components.

Thread 4.
Studies of realization of challenging signal processing applications Typical for the applications in question is that it is initially unknown whether it is at all possible to meet their demands with state-of-the-art technology or foreseeable new technology. Goal: For particular such application(s), acquire understanding of the demands that it puts on computer architectures, and possibly propose architecture solutions for the processing. The method is to investigate the computational flow, with its associated processing, memory and bandwidth demands, etc. The results of these studies will be exploited in further, more detailed architecture studies.

Thread 5.
Test and demonstration on parallel platform Goal: To demonstrate, test, integrate, and evaluate the (partial) results of the above threads on a common, flexible, parallel platform.

Thread 6.
Joint knowledge development within parallel/reconfigurable computing Goal: To give key personnel of the partners up-to-date knowledge of important trends, develop-ments, research results, industrial products, methods and tools.

 

Updated 2008-02-08